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Flexible Multi-Protocol Configurable Phy IP Cores

Configurable IP Cores

The TITAN II® platform is designed to fulfill the requirements of design engineers that need multiple high speed interfaces. The universal Phy IP cover a wide range of data transmission, bus width, and CDR and ability to meet the needs of a wide variety of ASIC/SoC designs. Titan II

Benefits:
  • Supports both CML and LVDS I/O –Programmable
  • Adjustable for wide applications
  • Low voltage 1.0, 1.2 V core, 1.8 V I/O
  • Data Range 622 Mbps to 6.375 Gbps
Features:
  • 8/10/16/20 bit used interface
  • (CDR) Clock Data Recovery - Disabled in SSM Mode
  • Power Management
  • Data Rate 622 Mb/s to 6.375 Gbps
  • Clock support 20 MHz to 800 MHz
  • Adjustable pre-emphasis and equalization
  • TSMC 130-90-65 nm process
  • Supports both CML and LVDS I/Os - Programmable
  • Adjustable for wide applications
    Low voltage 1.0, 1.2 V core, 1.8 V I/O
    Data Range 622 Mbps to 6.375 Gbps
TaraCom Solutions of SerDes IP Technology

 

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