PCI Express (PCIe) Phy IP Core

PCIe IP Core

TaraCom’s small size and low power PCI-Express Gen 2 core enables low-cost FPGA and ASIC designs. The IP core has been specifically designed for easy integration into multiple design applications.

The core is provided with a comprehensive verification suite that allow designers to fully validate the performance using low cost test equipment. Customization and integration services are available to meet your full requirements including TSMC 90, 65 and 45 nm.

  • PMA: Serializer/Deserializer / Rx / Tx / Clock Recovery
  • PCS: Encoder/Decoder/Deskew - 8-bit and 16-bit MAC interfaces
  • Wide range of PCI Express bus width x1, x4, x8, x16
  • Compliant with PCI Express Base Spec Rev 1.1
  • Supports 8-bit and 16-bit MAC interfaces
  • Supports PCI Express Power Management States
  • Serial and Parallel loop back test modes
  • PRBS for error checking
  • Supports Spread Spectrum Clock (SSC) Reference clock
  • Differential Reference - supports 100 MHz or 125 MHz
  • Serial I/O is high speed Current Mode Logic (CML, 5.0/2.5 Gbps)

PCI Express Phy Product Brief - TRC5024 TaraCom Solutions of SerDes IP Technology


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