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Serial GMII SerDes IP Core

SGMII

SGMII IP Phy is Serial Giga bit Media Independent Interface (SGMII) IP core and provides a single lane 1.25Gbps date rate interface to MAC layer and consists of Physical Convergent Sublayer (PCS) and Physical Media Dependent (PMD). SGMII IP transmitter includes Rate-Adaptation, Transmit state-machine and Serializer and transmitter IO blocks. The Receiver consists of Sampler, Clock Data Recovery (CDR) and high performance Phase-Lock Loop (PLL), Synchronization, Receive state-machine, and Rate adaptation blocks. The SGMII IP has a high performance rate Auto-negotiation block to negotiate rates between transmitter and receiver. The SGMII core is an ideal solution for applications requiring to connect the ASIC/SoC MAC to external 1000 BaseT Phy, where lowest power and pin counts is needed.

Features:
  • Supports Cisco Ver. 1.7 Serial-GMII specification
  • Single 1.0 V core supply
  • Supports GMII transfers
  • Jitter Generation below 0.2 UI, Jitter tolerance (CDR) exceed 0.72 IU
  • 1.25 Gbps Serial GMII interface
  • LVDS IO
  • At speed BIST SerDes Core
  • 1149.1 compatible JTAG port, and clause 22/45 MDIO interface

SGMII SerDes Product Brief - TRC1251 TaraCom Solutions of SerDes IP Technology

 

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