XAUI SerDes IP Core



The IP is a 10 Gb/s XAUI compliant interface with four independent channels supporting up to 3.125 Gb/s each. The XAUI interface, defined at 3.125 Gbps for 10 Gigabit Ethernet and 3.1875 Gbps for 10 Gigabit Fibre Channel, provides a 4-wide, 8b/10b-based intermediate speed channel extender interface for the transmission of 10 Gbps signals and is optimized for backplane applications.

These Phy IPs are based on an advanced analog architecture designed to scale to the next generation of data rates. The new high-speed SERDES XAUI is the de-facto standard for 3.125 Gbps backplanes, common implementation in chip-to-chip applications, and widespread adoption in the communications market.

  • Optimized for backplane applications
  • Per channel rates from 1.0625 to 3.125Gb/s
  • Jitter Tolerance > 0.72 U
  • Jitter Generation < 0.20 UI
  • 8b/10b encoders and decoders
  • Supports up to four levels of pre-emphasis and equalization
  • Synchronization for character alignment
  • 1149.1 compatible JTAG port, and clause 22/45 MDIO interface
  • Single 1.8V ±5% supply
  • TSMC advanced 90 and 65 nm CMOS process

XAUI SerDes Product Brief - TRC3114 TaraCom Solutions of SerDes IP Technology


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